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Optimized register level transfer mechanism for ASIC-based memscomputing

B. M. Shilpa 1, 2
B. M. Shilpa
, 
1 Sri Krishna Institute of Technology, 29 Hesarghatta Rd, Chikkabanavara, Bangalore, Karnataka 560090, India
2 Jagadguru Sri Shivarathreeshwara Academy of Technical Education, JSS Campus Rd, Srinivaspura, Bangalore, Karnataka 560060, India
3 Birla Institute of Technology and Science, Vidya Vihar, Pilani, Rajasthan 333031, India
Published 5 April 2024
Communication , Volume 10, Issue 1, 19-28
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Shilpa B. M., Shet S. K. Optimized register level transfer mechanism for ASIC-based memscomputing // Modern Electronic Materials. 2024. Vol. 10. No. 1. pp. 19-28.
GOST all authors (up to 50)
Shilpa B. M., Shet S. K. Optimized register level transfer mechanism for ASIC-based memscomputing // Modern Electronic Materials. 2024. Vol. 10. No. 1. pp. 19-28.
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TY - JOUR
DO - 10.3897/j.moem.10.1.113631
UR - https://moem.colab.ws/publications/10.3897/j.moem.10.1.113631
TI - Optimized register level transfer mechanism for ASIC-based memscomputing
T2 - Modern Electronic Materials
AU - Shilpa, B. M.
AU - Shet, Sathisha K.
PY - 2024
DA - 2024/04/05
PB - НИТУ МИСИС
SP - 19-28
IS - 1
VL - 10
ER -
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@article{2024_Shilpa,
author = {B. M. Shilpa and Sathisha K. Shet},
title = {Optimized register level transfer mechanism for ASIC-based memscomputing},
journal = {Modern Electronic Materials},
year = {2024},
volume = {10},
publisher = {НИТУ МИСИС},
month = {Apr},
url = {https://moem.colab.ws/publications/10.3897/j.moem.10.1.113631},
number = {1},
pages = {19--28},
doi = {10.3897/j.moem.10.1.113631}
}
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MLA
Shilpa, B. M., and Sathisha K. Shet. “Optimized register level transfer mechanism for ASIC-based memscomputing.” Modern Electronic Materials, vol. 10, no. 1, Apr. 2024, pp. 19-28. https://moem.colab.ws/publications/10.3897/j.moem.10.1.113631.
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Keywords

application specific integrated circuit (ASIC)
Buffalo-based register transfer level
functional verification
memcomputing

Abstract

Micro-electromechanical system-based semiconductor sensor systems typically need a reliable on-chip analog readout circuit to identify and process changes in physical properties. To improve the mobility, robustness, reliability and performance (in terms of power consumption and speed) of the sensor system, the remaining parts of the post-processing logic, such as the digital data processor (or part of it), can also integrated into the chip. Cost and integration are always important considerations in both analog and digital designs, but they become even more important; the subsystem of data processing must be squeezed into a very small space near the structure of the micro-electromechanical system (MEMS) sensor. The paper introduces a new Buffalo-based register-transfer level (BRTL) method that aims to improve the efficiency and reliability of the system of digital data processing for MEMS sensor post-processing algorithm. Initially, the memcomputing system was designed with the needed functional processing elements. Then, a novel Buffalo-based register-transfer level design is modelled in the MEMS architecture. The digital data transmission process is performed to estimate the reliability of the proposed BRTL model. Finally, the performance of the proposed model can be validated.

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